Semi-conductor components, e.g. corresponding integrated (analog and/or digital) computer circuits, semi-conductor memory components such as for instance function memory components (PLAs, PALs, etc.) and table memory components (e.g. ROMs or RAMs, particularly SRAMs and DRAMs) etc. are subjected to numerous tests during the course of the manufacturing process.
For the simultaneous manufacture of numerous (generally identical) semi-conductor components, a so-called wafer (i.e. a thin disk consisting of monocrystalline silicon) is used. The wafer is appropriately processed (e.g. subjected to numerous coating, exposure, etching, diffusion and implantation process steps, etc.), and subsequently sawn up (or for instance scored and snapped off), so that the individual components become available.
During the manufacture of semi-conductor components (e.g. DRAMs (Dynamic Random-Access Memories and/or dynamic Read/Write memories), particularly DDR-DRAMs (Double data Rate—DRAMs and/or DRAMs with double data rate)) the components (still on the wafer and incomplete) may be subjected to corresponding test procedures at one or several test stations by means of one or several test apparatuses (e.g. so-called kerf measurements at the scoring grid) even before all the required above processing steps have been performed on the wafer (i.e. even while the semi-conductor components are still semi-complete).
After the semi-conductor components have been completed (i.e. after all the above wafer processing steps have been performed) the semi-conductor components are subjected to further test procedures at one or several (further) test stations—for instance the components—still present on the wafer and completed—may be tested with the help of corresponding (further) test apparatuses (“disk tests”).
In corresponding fashion, several further tests may be performed (at further corresponding test stations and by using corresponding further test equipment) e.g. after the semi-conductor components have been installed in corresponding semi-conductor-component housings, and/or e.g. after the semi-conductor component housings (together with the semi-conductor components installed in them) have been installed in corresponding electronic modules (so-called “module tests”).
While testing the semi-conductor components (e.g. during the above disk tests, module tests, etc.), test procedures such as for instance “DC tests” and/or “AC tests” can be applied.
During a DC test for instance a voltage (or current) at a specific—in particular a constant—level may be applied to corresponding connections of a semi-conductor component to be tested, whereafter the level of the—resulting—currents (and/or voltages) are measured—in particular tested to see whether these currents (and/or voltages) fall within predetermined required critical values.
During an AC test in contrast, voltages (or currents) at varying levels can for instance be applied to the corresponding connections of a semi-conductor component, particularly corresponding test sample signals, with the help of which appropriate function tests may be performed on the semi-conductor component in question.
With the aid of above test procedures, defective semi-conductor components and/or modules may be identified and then removed (or else also partially repaired), and/or the process parameters—applied during the manufacture of the components in each case—may be appropriately modified and/or optimized in accordance with the test results achieved, etc., etc.
In the case of numerous applications—e.g. in server or workstation computers, etc., etc.—memory modules with data buffer components (so-called buffers) connected in series before them, e.g. so-called “buffered DIMMs”, may be used.
Memory modules of this nature generally contain one or more semi-conductor memory components, particularly DRAMs, as well as one or more data buffer components connected in series before the semi-conductor memory components (which may for instance be installed on the same printed circuit board as the DRAMs).
The memory modules are connected—particularly with a corresponding memory controller connected in series (e.g. arranged externally to the memory module in question)—with one or several micro-processors of a particular server or work station computer, etc.
In “partially” buffered memory modules, the address and control signals—e.g. emitted by the memory controller, or by the processor in question—may be (briefly) retained by corresponding data buffer components and then relayed—in chronologically co-ordinated, or where appropriate, in multiplexed or de-multiplexed fashion—to the memory components, e.g. DRAMs.
In contrast, the (useful) data signals—emitted by the memory controller and/or by each processor—may be directly—i.e. without being buffered by a corresponding data buffer component (buffer)—relayed to the memory component (and—conversely—the (useful) data signals emitted by the memory components may be directly—without a corresponding data buffer component (buffer) being connected in series before it—relayed to the memory controller and/or to the processor in question).
In “fully buffered” memory modules in contrast, the address and control signals, as well as the corresponding (useful) data signals exchanged between the memory controller and/or each processor and the memory components, can first be buffered by corresponding data buffer components before being relayed to the memory component and/or memory controller or to the processor in question.
If the above buffered memory module (or any other memory module) is subjected to a corresponding module test (for instance for testing the soldered connections and conductive tracks on the memory module, for instance the conductive tracks between the memory components/data buffer components), appropriate so-called MBIST devices (MBIST=Memory Built In Self Test) can be used, and corresponding LFSR devices (LFSR=Linear Feedback Shift Registers), for instance MBIST and LFSR devices provided on the date buffering components.
In order to perform an appropriate module test, corresponding pseudo-random test (useful) data signals—exhibiting a particular pre-set data width—can be accordingly tapped at the LFSR devices and relayed via corresponding data lines to the memory components, so that corresponding quasi-random test (useful) data is stored in the memory components.
The (test) address and (test) control signals required in order to perform the corresponding module tests can be generated by the above MBIST devices and relayed via corresponding address and control lines to the memory components.
The above procedure (in particular the use of pseudo-random test data signals generated by the LFSR devices) has the effect that test (useful) data signals—generated by the LFSR devices—and present on the data lines, exhibit a relatively wide spectrum of differing frequencies and/or that the test (useful) data signals consist of a relatively broad band of mixed frequencies.
Due to the pre-set fixed data width of the pseudo-random test (useful) data signals provided by LFSR devices, only memory components of a particular kind (namely memory components with a data width which corresponds with that of the pseudo-random test (useful) data signals provided by the LFSR devices) can be tested with these signals. If memory components with a data width which differs from this are to be tested, other LFSR devices with correspondingly different pseudo-random test (useful) data signal data widths must be used.